An output file (with the extension .sdo), generated by the Quartus^® II Compiler. The Standard Delay Format is an industry-standard format.

SDF Output Files are automatically generated when you compile a design.

SDF Output Files contain timing delay information that allow you to perform back-annotation for simulation with VHDL simulators that use simulation libraries that are compliant with VITAL version 2.2b and version 3.0 (VITAL 95); back-annotation for simulation in Verilog HDL simulators; and timing analysis and resynthesis with EDIF simulation and synthesis tools. SDF Output Files that are generated for EDA simulation tools do not contain negative setup and hold times.

The Quartus II Compiler can generate SDF Output Files in SDF version 2.1 or 1.0 format.

The file name of an SDF Output File is the same as the user-defined name for the project or design entity.

If you specify settings in the EDA Tool Settings page of the Settings dialog box (Assignments menu), the Compiler places the generated SDF Output File into a tool specific directory within the current project directory. For EDA simulation tools, the SDF Output File is placed in the /<project directory>/simulation/<EDA simulation tool> directory. For EDA timing analysis tools, the SDF Output File is placed in the /<project directory>/timing/<EDA timing analysis tool>. If you specify Custom Verilog HDL or Custom VHDL in the EDA Tool Settings page for simulation or timing analysis, the SDF Output File is placed in /<project directory>/simulation/custom or /<project directory>/timing/custom.

You can also generate an SDF Output File by using the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu). You can use this command if you have already compiled the design and want to change the EDA tool settings and generate an SDF Output File for another EDA tool.

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