Library Mapping File (.lmf)

An ASCII text file (with the extension .lmf) used to map cells in EDIF Input Files (.edf), components in VHDL Design Files (.vhd), or modules in Verilog Design Files (.v) to corresponding Quartus^® II logic functions.

LMFs allow the Compiler to substitute Quartus II logic functions for the cells in EDIF Input Files, VHDL Design Files, and Verilog Design Files. LMFs also eliminate the need for the Compiler to extract the information on those cells or functions and allow the Compiler to substitute Quartus II logic functions for non-Quartus II logic functions. The logic function mappings in Altera-provided LMFs allow you to take advantage of family-specific macrofunctions.

All cells in EDIF Input Files, and some of the functions in VHDL Design Files and Verilog Design Files must be mapped to Altera^® logic functions in an LMF so that the Compiler can interpret them.

If a VHDL Design File contains VHDL primitives that have Component Declarations in the maxplus2 package (which is in the \quartus\libraries\vhdlnn\altera directory, where nn is "87" or "93"), you must specify maxplus2.lmf as the LMF for the VHDL Design File.

LMFs for EDIF Input Files are specified as Compiler input files when you specify an LMF in the File name box in the EDA Tool Input Settings dialog box, which is available from the EDA Tool Settings page of the Settings dialog box (Assignments menu). LMFs for VHDL Design Files are specified in the VHDL Input page of the Settings dialog box (Assignments menu), and LMFs for Verilog Design Files are specified in the Verilog HDL Input page of the Settings dialog box.

You can use one of the following Altera-provided LMFs generated by industry-standard EDA tools:

You can also create new custom LMFs for EDIF Input Files, VHDL Design Files, and Verilog HDL Design Files.