An ASCII text file (with the extension .vht) that is generated by the Quartus^® II software or with the Quartus II Text Editor or any other standard text editor. A VHDL Test Bench File contains an instantiation of the top-level design entity for a design and simulation input vectors and simulation output vectors. You can use a VHDL Test Bench File for simulation of a design with other EDA tools.

You can create a VHDL Test Bench File from a vector source file in the Quartus II software by choosing the Export command (File menu) and exporting the file as a VHDL Test Bench File. You can also generate a template for a VHDL Test Bench File by compiling a design and choosing the EDA Tools Post Compilation Commands > Generate Test Bench Template command (Processing menu), which places the template in the /<project directory>/simulation/<EDA simulation tool> directory.

A VHDL Test Bench File is the same as a standard VHDL test bench file, saved with a .vht extension.

Back to Top