EDA Interfaces

Verilog HDL Output Settings Dialog Box
NOTE You open this dialog box by selecting a Verilog HDL simulation or timing analysis tool in the EDA tools list in the EDA Tool Settings page of the Settings dialog box (Assignments menu) and clicking Settings. The Generate Power Input File option is available only if you specify the Model Technology ModelSim software as the Simulation tool.

Allows you to specify options for generating Verilog Output Files (.vo) and Standard Delay Format Output Files (.sdo) for use with other EDA tools.

Pointer Click any item in this dialog box for information on that item:


Verilog HDL Output Settings Simulation tool Flatten buses into individual nodes Map illegal Verilog HDL characters Output Excalibur stripe as a single entity OK Cancel Reset Generate Power Input File Time Scale Truncate long hierarchy paths Bring out device-wide set/reset signals as ports Maintain hierarchy Generate SDF Output File

 

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