See Also

Directs the Quartus^® II software to include power estimation information in the Verilog Output File (.vo) or VHDL Output File (.vho) for a Verilog HDL or VHDL design after compiling the design in the Quartus II software. You can then perform a simulation in the ModelSim^® software to generate power estimation data.

Once you have simulated the design in the ModelSim software, a Power Input File (.pwf) is generated for the design and placed in the \<project directory>\simulation\modelsim directory. You can then use this file for performing power estimation of the design in the Quartus II Simulator.

This option is available for use with only APEX™ 20KE, APEX 20KC, ARM®-based Excalibur™, and Mercury™ devices.