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To specify options for generating VHDL Output Files (.vho) and Standard Delay Format Output Files (.sdo) for use with other EDA tools:

1. If you have not already done so, create a new project or open an existing project.

2. Choose Settings (Assignments menu).  Shortcut.

3. In the Categories list, select EDA Tool Settings.

4. In the EDA tools list, select Simulation or Timing analysis.

5. In the Tool name list, select the name of a Verilog HDL simulation or timing analysis tool, or select Custom VHDL.  More Details

6. Click Settings.

7. In the VHDL Output Settings dialog box, make sure you selected the correct Simulation tool or Timing analysis tool.

8. If you want to truncate hierarchical node names to 80 characters or less, turn on Truncate long hierarchy paths.

9. If you want to flatten all buses in the VHDL Output File, turn on Flatten buses into individual nodes.

10. If you want to map the illegal VHDL characters in the VHDL Output File, turn on Map illegal VHDL characters.

11. If you are targeting an ARM^®-based Excalibur^™ device and you want to perform a full stripe model simulation of the design,, turn on Output Excalibur stripe as a single entity.

12. If you want to perform power estimation using the Model Technology^™ ModelSim^® software, turn on Generate Power Input File.

13. If you want to add the devpor, devclrn, and devoe signals as input ports in the top-level design hierarchy in the VHDL Output File, turn on Bring out device-wide set/reset signals as ports.

14. If you want to maintain the original design hierarchy in the VHDL Output File, turn on Maintain hierarchy.

15. If you will be performing a timing simulation with the VHDL Output File, turn on Generate SDF Output File. If you will be performing a functional simulation, make sure Generate SDF Output File is turned off.

16. If you want to restore the default VHDL output settings for the simulation or timing analysis tool, click Reset.

17. Click OK. More Details

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