See Also

Specifies the EDA tool you are using for timing analysis. If you select a specific EDA tool, the Compiler selects the default Verilog HDL output settings or VHDL output settings for that tool. You can change all of the settings in this dialog box, and you can click Reset to restore settings to the original defaults for your timing analysis tool. If you have defined customized settings previously, you can select Custom VHDL or Custom Verilog HDL to use those option settings.