See Also

Directs the Compiler to generate an Standard Delay Format Output File (.sdo) for the project.

Turn this option on to generate a VHDL Output File (.vho) or Verilog Output File (.vo) for timing simulation with other EDA tools. Turn this option off to generate a VHDL or Verilog Output File for functional simulation with other EDA tools, and an SDF Output File will not be generated.