EDA Interfaces

VHDL Output Settings Dialog Box
NOTE You open this dialog box by selecting a VHDL simulation or timing analysis tool in the EDA tools list in the EDA Tool Settings page of the Settings dialog box (Assignments menu) and clicking Settings. The Generate Power Input File option is available only if you specify the Model Technology ModelSim software as the Simulation tool.

Allows you to specify options for generating VHDL Output Files (.vho) and Standard Delay Format Output Files (.sdo) for use with other EDA tools.

Pointer Click any item in this dialog box for information on that item:


VHDL Output Settings Simulation tool Truncate long hierarchy paths Flatten buses into individual nodes Map illegal VHDL characters Output Excalibur stripe as a single entity OK Cancel Reset Generate Power Input File Bring out device-wide set/reset signals as ports Maintain hierarchy Generate SDF Output File

 

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