Settings Command (Assignments Menu)
Procedures
Overviews
Adding & Deleting Global Project Parameters
Adding & Removing Files
Generating Files for HardCopy Devices
Opening the Settings Dialog Box
Registering for and Receiving Stratix GX Information
Specifying Settings for Default Logic Options
Specifying Software Toolset Directories
Specifying the Library Mapping File for Compiling or Simulating Verilog HDL Input Files
Specifying the Library Mapping File for Compiling or Simulating VHDL Input Files
Specifying the Verilog HDL Version for Compiling or Simulating Verilog HDL Input Files
Specifying the VHDL Version for Compiling or Simulating VHDL Input Files
Specifying User Libraries
Compiling Designs
Generating HardCopy Files
Making Assignments
Simulating Designs
Specifying Compiler Settings
Specifying Simulator Settings
Specifying Software Build Settings
Using the Design Assistant
Using the Quartus II Software with Other EDA Tools
Using the Software Builder
Using the Timing Analyzer
Working with Quartus II Projects
Allows you to specify and save project settings.
Click any item in this picture for information on that item:
Back to Top
- PLDWorld -
Created by
chm2web
html help conversion utility.
