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You can use the Quartus® II Simulator to simulate any design in a project. Depending on the type of information you need, you can perform a functional simulation to test the logical operation of your design, or you can perform a timing simulation to test both the logical operation and the worst-case timing for the design in the target device. In addition, there are special instructions for simulating under the following conditions:
If you want to simulate one or more bidirectional nodes, refer to Guidelines for Simulating Bidirectional Nodes.
If you want to simulate a device-wide output enable pin, refer to Simulating a Device-Wide Output Enable Pin.
If you want to simulate a device-wide reset pin, refer to Simulating a Device-Wide Reset Pin.
If you want to simulate a design that contains an embedded processor core, refer to Simulating an Embedded Processor.
The Quartus II software allows you to simulate an entire design, or to simulate any part of a design. You can designate any design entity in a project as the "simulation focus," which is the design entity that you want to simulate. When you simulate the design, the Simulator simulates the simulation focus and all of its subordinate design entities.
You specify the simulation focus, the type of simulation that should be performed, the time period covered by the simulation, the source of vector stimuli, and other simulation options by creating Simulator settings. You can create your own customized groups of Simulator settings, or you can use the default Simulator settings that are generated automatically each time you create a new project. To designate which Simulator settings should be used for the current simulation, you specify the current Simulator settings.
Before starting a simulation, you must create and specify a vector source file as the source of simulation input vectors. The Simulator uses the input vectors contained in the vector source file to simulate the output signals that a programmed device would produce under the same conditions. You can create a Vector Waveform File (.vwf) and open a MAX+PLUS® II-style Vector File (.vec) with the Quartus II Waveform Editor. In addition, you can create one or more breakpoints that will interrupt the simulation for debugging purposes. You can use the following commands to begin a functional or timing simulation:
With the Initialize Simulation command (Processing menu), the Simulator extracts and loads the simulation netlist. In a functional simulation, the simulation netlist is composed of flattened netlists extracted from the design files. In a timing simulation, the simulation netlist is extracted from the Compiler database netlist, which includes timing information. When initialization is complete, the Simulator pauses, allowing you to update embedded memory or run a Tcl script.
With the Run Simulation command (Processing menu), the simulation progresses until simulation is complete, or until the Simulator encounters a breakpoint. When simulation is complete, the Simulator generates a message. You can stop and cancel the simulation at any time by choosing the Stop Processing command (Processing menu).
During simulation, the Simulation Report window appears automatically. The Simulation Report displays useful information about the current simulation, including waveforms of the simulation outputs. Go to Viewing the Results of a Compilation or Simulation in the Report Window for more information on viewing simulation results.
If you want to resimulate a design without using any previous simulation information that may exist in the database, specify the design's Simulator settings as the current Simulator settings and choose Purge Simulator Results from Database (Processing menu). You can also use the Purge Simulator Results from Database command to delete simulation results that you no longer need. When you purge simulation results from the database, you lose all results from the design's simulation, including the Simulation Report.
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