Procedures

Commands

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You can use the Design Assistant to check the reliability of a design based on a set of design rules. The Design Assistant is especially useful for checking the reliability of a design before converting the design for HardCopy^™ devices.

The Design Assistant supports designs that target any Altera^® device supported by the Quartus^® II software except a MAX^® 3000 and MAX 7000 device.

The Design Assistant can use the following rules to analyze the design:

• All data bits that are transferred between asynchronous clock domains are synchronized
• Asynchronous load should be directly supported by one logic cell
• Clock signal should be a global signal
• Clock signal source should drive only input clock ports
• Data bits are not correctly synchronized when transferred between asynchronous clock domains
• Data bits are not synchronized when transferred between asynchronous clock domains
• Design should not contain combinatorial loops
• Design should not contain delay chains
• Design should not contain latches
• Design should not contain SR latches
• External reset should be correctly synchronized
• External reset should be synchronized using two cascaded registers
• Gated clock should be implemented according to Altera standard scheme
• Gated reset should be synchronized
• Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized
• Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized
• Input clock pin should fan out to only one gated clock
• Inverter should not be implemented in logic cell
• Multiple pulses should not be generated in design
• Nodes with high fan-out
• Only one VREF pin should be assigned to HardCopy test pin in an I/O bank
• Pulses should be implemented according to Altera standard scheme
• Register output directly drives input of another register when both registers are triggered at same time
• Register output should not drive register's control signal directly or through combinatorial logic
• Registers are triggered by different edges of same clock
• Registers in direct data transfer between clock domains are triggered by clock edges at the same time
• Reset signal source should drive only input reset ports
• Two or more register outputs in cascade should not directly drive clock ports of following registers

You can use the Design Assistant rules list in the Design Assistant page of the Settings dialog box (Assignments menu) to specify which rules you want the Design Assistant to apply to a design. If you turn on Nodes with high fan-out, Report all nodes with more than <n> fan-outs, and/or Report top <n> nodes with the highest fan-out in the Design Assistant rules list, you can use the High-Fanout Net Settings dialog box, which is available from the Design Assistant page, to specify the nodes you want the Design Assistant to report. The Design Assistant Settings section of the Compilation Report window lists all the Design Assistant rules, and indicates which rules you turn on and the settings you specify.

You can run the Design Assistant during a compilation or an analysis and synthesis of a design by turning on any Design Assistant rule or category in the Design Assistant rules list. When you compile the design, the Design Assistant performs a post-fitting analysis, that is, the Design Assistant analyzes the netlist that the Compiler generates for the design during fitting. When you perform an analysis and synthesis on the design, the Design Assistant performs a post-synthesis analysis; that is, the Design Assistant analyzes the netlist that the Compiler generates for the design during logic synthesis.

You can also run the Design Assistant after a successful compilation or a successful analysis and synthesis using the Start > Start Design Assistant command (Processing menu). When you start the Design Assistant after performing a compilation, the Design Assistant performs a post-fitting analysis on the design. When you start the Design Assistant after performing an analysis and synthesis, the Design Assistant performs a post-synthesis analysis on the design.

The Design Assistant generates warning messages when the design does not follow a design rule, and generates information messages to provide information regarding a design rule. Both types of messages appear in the Messages window, and in the Messages section of the Compilation Report window. The Design Assistant Results section of the Compilation Report window also lists information for each instance that a rule is not followed, and any nodes you directed the Design Assistant to report. In addition, if you turn on More than one VREF pin is assigned to HardCopy test pin in an I/O bank in the Design Assistant rules list, and the Design Assistant finds violation(s) of this rule, the HardCopy Test Pins section of the Compilation Report window lists all the test pins in a HardCopy device.

For more information about the Report window sections, go to Overview: Viewing the Results of a Compilation or Simulation in the Report Window

The Design Assistant classifies messages using the following four severity levels:

The Design Assistant Results section lists the severity of each rule violation. In addition, the Design Assistant Summary section of the Compilation Report window lists the number of messages that the Design Assistant generated for each severity level.

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