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In a design, the data bits that are transferred between asynchronous clock domains should be synchronized.
If the data bits belong to single-bit data, the synchronization of the data bits should follow the following guidelines to avoid metastability problems:
Each data bit should be synchronized with two cascading registers in the receiving asynchronous clock domain.
The cascading registers should be triggered on the same clock edge.
There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
If the data bits belong to multi-bit data, the synchronization of the data bits should follow the following guidelines to avoid metastability problems:
Only the data bits that act as REQ (Request) and/or ACK (Acknowledge) signals should be synchronized.
The data bits that act as REQ and ACK signals should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.
The cascading registers should be triggered on the same clock edge.
There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
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