See Also

An external reset, which is a primary input that is used as a reset signal, should be synchronized in a design (that is, it should drive two cascaded registers before driving one or more input reset ports of other registers). In a design, an asynchronous reset can affect the recovery time of a register, cause stability problems, and reset state machines to incorrect states.

The synchronized gated reset should follow the following guidelines:

• The external reset should be synchronized with two cascaded registers.

• There should be no logic between the two cascaded registers.

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