See Also

A design should not contain structures that generate multiple pulses in the following way:

• Each structure contains a 2-input AND, NAND, OR, or NOR gate.

• The AND or OR gate output drives one of the gate's own inputs through an inverted delay chain (two or more consecutive nodes with a single fan-in and a single fan-out that are used to cause delay).

  or

  The NAND or NOR gate output drives one of the gate's own inputs through a delay chain.

• A triggering signal drives the gate's other input.

These structures generate widths for the multiple pulses that are difficult for the Quartus^® II software to determine, set, or verify. For example, the pulse widths are difficult for the Quartus II software to determine if the Fitter and Logic Synthesizer have not already determined the node delays necessary for the pulse widths. Also, when a design is converted for a HardCopy^™ device, the generated pulse widths may be different than the pulse widths generated by the design's original device.

Structures that generate multiple pulses cause more problems than pulse generators because of the number of pulses involved. In addition, when the structures generate multiples pulses, they also increase the frequency of the design.

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