See Also

A pulse generator in a design should not generate pulses in one of the following ways:

• By increasing the width of a glitch using a 2-input AND, NAND, OR, or NOR gate, where the source for the two gate inputs are the same, but the design inverts the source for one of the gate inputs.

• Using a register where the register output drives the register's own asynchronous reset signal through an delay chain (two or more consecutive nodes with a single fan-in and a single fan-out that are used to cause delay).

These pulse generators do not follow the Altera^® standard scheme, where the generated pulse width is always equal to the clock period. As a result, the pulse widths are difficult for the Quartus^® II software to determine, set, or verify. For example, the pulse width generated by a pulse generator that uses a 2-input AND gate depends on the relative delays of the path that drives the AND gate directly and the path that the design inverts before driving the AND gate. Also, when a design is converted for a HardCopy^™ device, the generated pulse width may be different than the pulse width generated by the design's original device.

The following image shows an example of a pulse generator that follows the Altera standard scheme:

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