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In a design, a gated reset (which is combinatorial logic used as a reset signal) that is generated in one clock domain and used in one or more other, asynchronous clock domains should follow the following guidelines:

• The gated reset should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.

• The cascading registers should be triggered on the same clock edge.

• There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

An incorrectly synchronized gated reset may cause metastability problems in the design.

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