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Specifies which of the following rules you want the Design Assistant to apply when analyzing and generating messages for the current ACEX^® 1K, APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, FLEX^® 6000, FLEX 10KE, Mercury^™, Stratix^™, or Stratix^™ GX design:

• Clock
  • Gated clock should be implemented according to Altera^® standard scheme
  • Inverter should not be implemented in logic cell
  • Input clock pin should fan out to only one gated clock
  • Clock signal source should drive only input clock ports
  • Clock signal should be a global signal
  • Registers are triggered by different edges of same clock
• Reset
  • Gated reset should be synchronized
  • External reset should be synchronized using two cascaded registers
  • External reset should be correctly synchronized
  • Reset signal source should drive only input reset ports
  • Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized
  • Gated reset that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized
• Timing Closure
  • Nodes with high fan-out
  • Register output directly drives input of another register when both registers are triggered at same time
  • Registers in direct data transfer between clock domains are triggered by clock edges at the same time
• Non-synchronous design structure
  • Design should not contain combinatorial loops
  • Register output should not drive register's control signal directly or through combinatorial logic
  • Design should not contain delay chains
  • Two or more register outputs in cascade should not directly drive clock ports of following registers
  • Pulses should be implemented according to Altera standard scheme
  • Multiple pulses should not be generated in design
  • Design should not contain SR latches
  • Design should not contain latches
• Asynchronous clock domains
  • Data bits are not synchronized when transferred between asynchronous clock domains
  • All data bits that are transferred between asynchronous clock domains are synchronized
  • Data bits are not correctly synchronized when transferred between asynchronous clock domains
• HardCopy^™ rules
  • Asynchronous load should be directly supported by one logic cell
  • Only one VREF pin should be assigned to HardCopy test pin in an I/O bank

If you turn on any of the rules or categories, you direct the Quartus^® II software to automatically run the Design Assistant when you compile or perform an analysis or synthesis on the current design.

If you turn on a rule category, such as Clock or Design Assistant configuration rule names, all the rules and categories under that category are automatically turned on. If you turn on a rule or category under one or more upper-level categories, the upper-level category or categories are automatically turned on. Similarly, if you turn off a rule category, all the rules and categories under that category are automatically turned off. If you turn off all the rules and categories under one or more upper-level categories, the upper-level category or categories are automatically turned off.

If you turn on Nodes with high fan-out, Report all nodes with more than <n> fan-outs, and/or Report top <n> nodes with the highest fan-out, you must use the High-Fanout Net Settings dialog box, which is available from the Design Assistant page of the Settings dialog box (Assignments menu), to specify the nodes you want the Design Assistant to report.

The Design Assistant Settings section of the Compilation Report window lists all the Design Assistant rules, and indicates which rules you turn on.

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