An Altera^® device family designed as a cost-effective solution for data path applications. The Cyclone^™ device architecture supports M4K memory blocks to implement dual-port memory and true dual-port memory and high-speed interfaces to external memory devices such as single data rate (SDR) SDRAM and double data rate (DDR) SDRAM. The Cyclone family includes the EP1C3, EP1C6, EP1C12, and EP1C20 devices.

Cyclone devices provide up to 2 PLLs per device, which provide advanced multiplication, programmable duty cycle, and phase shifting. Cyclone devices also provide up to 8 global clocks with 6 clocking resources per device region.

Cyclone devices support numerous single-ended and differential I/O standards, including LVCMOS, LVDS, LVTTL, PCI, SSTL-2 Class I & II, and SSTL-3 Class I & II.

The memory blocks of a Cyclone device can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers.

Cyclone devices support active serial configuration mode with an EPCS1 or EPCS4 serial configuration device. When performing active serial configuration, the first device in a chain of devices must be a Cyclone device.

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