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Two or More Register Outputs in Cascade Should Not Directly Drive Clock Ports of Following Registers (Design Assistant Rule)



A design should not contain ripple clock structures, that is, structures where the outputs of two or more registers in a cascade each directly drives the input clock port of the following register in the cascade. Cascading registers should have only one output, or no output, that directly drives the following register's input clock port. The following image shows an example of a ripple clock structure:


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