An Altera^® device family based on a scalable high-performance architecture. The Stratix^™ device architecture supports the TriMatrix^™ Memory architecture, consisting of three RAM block sizes, the M512 and M4K memory blocks and the M-RAM, to implement dual-port memory and true dual-port memory. Stratix devices offer support for remote configuration updates, and contain embedded DSP blocks that enable efficient implementation of high-performance filters and multipliers.

Stratix devices support multiple I/O transfer protocols, for example, RapidIO^™ and UTOPIA IV. These protocols provide high-speed communication with application specific standard products (ASSPs), application-specific integrated circuits (ASICs), and other programmable logic devices (PLDs).

Stratix devices provide up to 12 PLLs per device, which provide clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting. Stratix devices also provide a hierarchical clocking structure with high-speed performance and up to 16 global clocks with 22 clocking resources per device region.

Stratix devices support numerous single-ended and differential I/O standards, including Compact PCI, Differential HSTL, Differential SSTL-2, GTL, LVPECL and SSTL-18 Class I & II. Additionally, Terminator^™ technology provides on-chip termination for differential and single-ended I/O pins with impedance matching.

The memory blocks of a Stratix device can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers. These blocks can also emulate SERDES functions for low-speed LVDS channels. In addition, Stratix devices provide high-speed interfaces to external memory devices such as single data rate (SDR) SDRAM, double data rate (DDR) SDRAM, DDR II SDRAM, DDR fast cycle RAM (FCRAM), quad data rate (QDR) SRAM, and zero bus turnaround (ZBT) SRAM.

You can use device migration to transfer a design between Stratix devices with equivalent pin-outs, while maintaining the same board layout and pin assignments.

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