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A design should not contain latches, which are structures where two NOR or NAND gates (which the Quartus^® II software implements in logic cells) are cross-coupled using combinatorial loops that drive the output of one gate to an input of the other gate. These latches can cause glitches and ambiguous timing in a design, which makes timing analysis of the design more difficult.

The Design Assistant generates this rule when it identifies one or more structures as latches but cannot determine the latch types. The latches may also be part of more sophisticated latches that the Design Assistant cannot identify.

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