Procedures

Commands

See Also

The Quartus^® II Timing Analyzer allows you to analyze the performance of all logic in your design. After timing analysis, you can then list the timing paths and locate them in the floorplan, to determine critical speed paths and paths that limit the design's performance.

The timing analysis runs automatically at the end of the compilation process. After first-time compilation, you can run the Timing Analyzer again separately by choosing Start > Start Timing Analysis (Processing menu).

In the Quartus II software, you can specify timing requirements and options that apply to the entire project, to specific design entities, or to individual nodes and pins. For example, you can specify project-wide or individual timing requirements for the maximum frequency (f_MAX), setup time (t_SU), hold time (t_H), clock-to-output delay (t_CO), and pin-to-pin delay (t_PD). You can specify all project-wide timing requirements and settings easily with the Timing wizard. Alternatively, you can use the Settings command (Assignments menu) to specify project-wide timing requirements and options without using the wizard.

You can also assign timing requirements to individual entities, nodes, and pins with the Assignment Organizer command (Assignments menu). In addition, you can override the specified default required f_MAX for individual clock signals in the design by creating clock settings and assigning them to individual clock signals in the design. If you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device to meet your timing goals if you use timing-driven compilation.

After you run a timing analysis, you can view the timing analysis results in the Timing Analyses folder of the Compilation Report. By default, the Timing Analyzer analyzes and reports the f_MAX of every register, the t_SU and t_H of every input register, and the t_CO of every output register in the compiled design entity. In addition, the Timing Analyzer analyzes all pin-to-pin paths and reports the t_PD between pins. The Timing Analyzer reports the timing analysis results for designs without timing requirements or complex timing assignments in the fmax, Register-to-Register Fmax, tsu, th, tco, tpd, RSKM, and/or TCCS Compilation Report sections, respectively.

The Quartus II Timing Analyzer can also perform analysis on designs that use timing requirements or complex timing assignments. The Timing Analyzer reports these timing analysis results as slack values in the Clock Requirement, tsu Requirements, th Requirements, tco Requirements, tpd Requirements, tpd Minimum Requirements, and/or Hold Violations Requirement section of the Compilation Report, respectively.

	More information is available on Timing Analysis on the Altera® web site.

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