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Reports the worst-case minimum point-to-point delays (t_PD) between the source and destination points. The Timing Analyzer generates a tpd Minimum Requirements section for all designs that include one or more valid individual Minimum Delay Requirement timing assignments. You can use the Assignment Organizer (Assignments menu) to assign the Minimum Delay Requirement timing assignment to a path in a design. The tpd Minimum Requirements section reports the timing analysis results in a resizable, multicolumn table.

The Timing Analyzer generates the tpd Minimum Requirements section only when the design contains one or more valid individual Minimum Delay Requirement timing assignments. Otherwise, the Timing Analyzer reports the tPD information in the tpd section.

The tpd Minimum Requirements section lists the specified Minimum Delay Requirement value, the actual minimum delay achieved, and the worst-case slack times. A positive slack value, displayed in black, indicates the margin by which a timing requirement was achieved. A negative slack value, displayed in red, indicates the margin by which the requirement was not achieved. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

The following figure shows an excerpt from the tpd Minimum Requirements section of a sample design:

You can select a source or destination node name in the tpd Minimum Requirements section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose List Paths, the time increments that comprise the delay path appear in the Messages window. You can locate the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Minimum slack time is <delay value> ns between <source node type> <source node name> and <destination node type> <destination node name> 
    + Longest register to register delay is <delay value> ns
       1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    - Minimum register to register requirement is <Minimum Delay Requirement value> ns
            

The Timing Analyzer calculates the minimum t_PD slack using the following equation:

minimum t_PD slack = <actual minimum point-to-point time> - <required minimum point-to-point time>

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