See Also

Reports the actual transmitter channel-to-channel skew (TCCS) for the data output pin, transmitter channel, and clock in each LVDS circuit in the design. For Stratix^™ or Stratix^™ GX designs, the Timing Analyzer reports only the maximum TCCS for all channels. TCCS is the timing difference between the fastest and slowest output transitions, including t_CO variations and clock skew. You can click the + icon next the data pin name to expand the table and display the transmitter channel and clock names in the LVDS circuit.

The following figure shows an excerpt from the TCCS section of a sample design:

You can select a data pin, transmitter channel, or clock name in the TCCS section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the clock. You can locate the source of a delay path in the design file by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

LVDS channel-to-channel skew for data out pin <name>, LVDS transmitter channel <name> , and clock out pin <name> is <time> ns
    Delay from clock to LVDS transmitter data output <name> is <time> ns
    Delay from clock to LVDS transmitter clock output <name> is <time> ns

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