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For designs that use complex timing assignments, the Timing Analyzer generates a Clock Requirement section that reports the worst-case speed performance for each clock analyzed in the design. This timing information is displayed in a resizable, multicolumn table. Each Clock Requirement section reports the required setup relationship, the required maximum point-to-point time, the actual maximum point-to-point time, and the slack of the 10 slowest timing requirement paths. A positive slack value, displayed in black, indicates the margin by which a timing requirement was achieved. A negative slack value, displayed in red, indicates the margin by which the requirement was not achieved. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

The Timing Analyzer generates the Clock Requirement section only when your design contains complex timing assignments. Otherwise, the Timing Analyzer reports the maximum speed performance information in the fmax section.

The following figure shows an excerpt from the Clock Requirement section of a sample design:

You can select a source or destination node in the Clock Requirement section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the clock. You can locate to the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Slack time is <delay value> ns for clock <clock name> between register <source register name> and register <destination register name>
    + Largest register to register requirement is <frequency requirement> ns
        + Setup requirement between source and destination is <setup requirement> ns
        + Largest Clock skew is <clock skew value> ns
            + Shortest Clock path from <clock name> to destination register is <delay value> ns
                1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
            - Longest Clock path from <clock name> to destination register is <delay value> ns
                1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
        - Micro clock to output delay of source register is <delay value> ns
        - Micro setup delay of destination register is <delay value> ns
    - Longest register to register delay is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>

The Timing Analyzer calculates the slack using the following equation:

slack = <required maximum point-to-point time> - <actual maximum point-to-point time>

The Timing Analyzer calculates the setup slack using the following equation:

setup slack = (<setup relationship>) - (<maximum clock pin to source register delay> + <t_CO of source register> + <register-to-register delay> + <t_SU of destination register> - <minimum clock pin to destination register delay>)

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