The maximum acceptable delay for a given pin-to-register, register-to-register, or register-to-pin path. In designs with "complex timing assignments," the Timing Analyzer uses the specified timing requirements and the "setup relationship" to calculate the required maximum point-to-point time in order to determine the "slack" time.
If a pair of source and destination nodes have multiple timing requirement assignments, the required maximum point-to-point time represents the most stringent timing requirement.
The required maximum point-to-point time is calculated to determine the timing requirement using the following equations:
| Delay Path | Requirement Calculation |
|---|---|
| Pin-to-register delays |
requirement = <tSU requirement> + <minimum clock pin to register delay> - <tSU of destination register>requirement = <tPD requirement> |
| Register-to-pin delays |
requirement = <tCO requirement> - <tCO> - <maximum clock pin to register delay>
requirement = <tPD requirement> |
| Register-to-register delays |
requirement = (<worst case tSU relationship>) + ([multicycle - 1] x <clock period> - (<tCO of source> + <tSU of destination register>) - <maximum clock pin to source register delay> + <minimum clock pin to destination register delay>
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