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Reports any internal hold (t_H) violations of the minimum setup and hold requirements. An internal hold violation is usually the result of clock skew. The Hold Violations section reports the timing analysis results for any internal hold violations in a resizable, multicolumn table.

The Hold Violations section lists the required hold relationship as determined by the Quartus^® II software, the corresponding required minimum point-to-point time, and the actual minimum point-to-point time achieved during timing analysis. The Hold Violations section also lists the negative slack times associated with the hold violation. The negative slack value, displayed in red, indicates the margin by which the requirement was not achieved.

The following figure shows an excerpt from the Hold Violations section of a sample design:

You can select a source or destination node in the Hold Violations section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose the List Paths command, the time increments that comprise the delay path appear in the Messages window. You can locate the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Minimum slack time is <delay value> ns for clock between register <source name> and register <destination name> 
    + Shortest register to register delay is <delay value> ns
       1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    - Smallest register to register requirement is <required minimum P2P time> ns
        + Hold requirement between source and destination is <hold requirement> ns
        + Smallest clock skew is <clock skew> ns
          + Longest clock path from <source clock> to destination register is <delay value> ns
              1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
           - Shortest clock path from <destination clock> to destination register is <delay value> ns
              1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
        - Micro clock to output delay of source is <delay value>
        + Micro hold delay of destination is <delay value> 

The Timing Analyzer calculates the minimum slack using the following equation:

Minimum slack = <actual minimum P2P time> - <required minimum P2P time>

The Timing Analyzer calculates the hold slack using the following equation:

hold slack = (<minimum clock pin to source register delay> + <t_CO of source> + <register to register delay> - <t_H of register> - <maximum clock pin to destination register delay>) - (<hold relationship>)

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