See Also

Reports the timing analysis results for any specified t_SU timing requirements. The Timing Analyzer generates a tsu Requirements section for all designs that include valid project-wide or individual t_SU requirements. The tsu Requirements section reports the timing analysis results in a resizable, multicolumn table. The tsu Requirements section lists the specified t_SU requirement(s), the actual t_SU achieved, and the 10 worst-case slack times. A positive slack value, displayed in black, indicates the margin by which a timing requirement was achieved. A negative slack value, displayed in red, indicates the margin by which the requirement was not achieved. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

The following figure shows an excerpt from the tsu Requirements section of a sample design:

You can select a source or destination node in the tsu Requirements section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose the List Paths command, the time increments that comprise the delay path appear in the Messages window. You can locate the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Slack time is <delay value> ns for clock <destination clock name> between pin <source pin name> and register <destination register name>
    + tsu requirement for source pin and destination register is <tSU requirement> ns
    - tsu from clock to input pin is <actual tSU> ns
        + Longest pin to register delay is <delay value>
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
        + Micro setup delay of destination is <delay value> ns
        - Shortest clock path from <destination clock> to destination register is <delay value> ns
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>

The Timing Analyzer calculates the t_SU slack using the following equation:

t_SU slack = <required tsu> - <actual tsu>

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