See Also

Reports the actual setup (t_SU) time for the input pins that feed the clock (or latch) enable and data or clock enable inputs to the destination register. The input setup time information is displayed in a resizable, multicolumn table. You can click the + icon next to the data pin name to expand the table and list, by default, the 10 slowest data pin to register paths. You can also click the + icon next to any register name to display the clock signal that feeds the register. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

If you specify any project-wide or individual tSU timing requirements, the Timing Analyzer also reports the tSU timing analysis results as slack values in the tsu Requirements section (Compilation Report).

The following figure shows an excerpt from the tsu section of a sample design:

You can select a data pin, register, or clock name in the tsu section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected item. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the data pin or register. You can locate to the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

tsu for register <register name> (Data Pin=<data pin name>,Clock Pin=<clock pin name>) is <value> ns
    + Longest pin to register delay is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    + Micro setup delay of destination register is <delay value> ns
    - Shortest Clock path from <clock name> to destination register is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>   

The Timing Analyzer calculates t_SU using the following equation:

t_SU = <pin to register delay> + <micro setup delay> - <clock to destination register delay>

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