See Also

Reports the actual clock to output (t_CO) time for all source clocks and destination output pins, as determined by the Timing Analyzer. The clock to output delay information is displayed in a resizable, multicolumn table. You can click the + icon next the output pin name to expand the table and list, by default, the ten register names that represent the slowest t_CO paths. You can also click the + icon next to any register name to display the clock signal that feeds the register. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

If you specify any project-wide or individual tCO timing requirements, the Timing Analyzer also reports the tCO timing analysis results as slack values in the tco Requirements section (Compilation Report).

The following figure shows an excerpt from the tco section of a sample design:

You can select an output pin, register, or clock name in the tco Report section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected item. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the output pin, register, or clock. You can locate to the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

tco from clock <clock name> through register <register name> is <delay value> ns
    + Longest Clock path from <clock name> to source register is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    + Micro clock to output delay of source register is <delay value> ns
    + Longest register to pin delay is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>   

The Timing Analyzer calculates t_CO using the following equation:

t_CO = <clock to source register delay> + <micro clock to output delay> + <register to pin delay>

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