See Also

Reports the timing analysis results for any specified t_H timing requirements. The Timing Analyzer generates a th Requirements section for all designs that include valid project-wide or individual t_H requirements. The th Requirements section reports the timing analysis results in a resizable, multicolumn table. The th Requirements section lists the specified t_H requirement(s), the actual t_H achieved, and the 10 worst-case minimum slack times. A positive slack value, displayed in black, indicates the margin by which a timing requirement was achieved. A negative slack value, displayed in red, indicates the margin by which the requirement was not achieved. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

The following figure shows an excerpt from the th Requirements section of a sample design:

You can select a source or destination node name in the th Requirements section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected node. When you choose the List Paths command, the time increments that comprise the delay path appear in the Messages window. You can locate the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Slack time is <delay value> ns for clock <destination clock name> between pin <source pin name> and register <destination register name> 
    + th requirement for source pin and destination register is <tH requirement> ns
    - th from clock to input pin is <actual tH> ns
        + Longest clock path from <destination clock name> to destination register is <delay value>
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
        + Micro hold delay of destination is <delay value> ns
        - Shortest pin to register delay is <delay value> ns
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>

The Timing Analyzer calculates the minimum t_H slack using the following equation:

minimum t_H slack = <required th> - <actual th>

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