See Also

Reports the longest and shortest point-to-point (t_PD) delay between the source and destination nodes. The t_PD delay information is displayed in a resizable, multicolumn table. You can increase or decrease the number of timing requirement paths displayed in the report by specifying options in the Timing Analysis Reporting page of the Settings dialog box (Assignments menu).

If you specify any project-wide or individual tPD timing requirements, the Timing Analyzer also reports the tPD timing analysis results as slack values in the tpd Requirements section (Compilation Report).

The following figure shows an excerpt from the tpd section of a sample design:

You can select a source or destination node in the tpd Report section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected path. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the selected node. You can locate to the source of the delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Longest tpd from source pin <pin name> to destination pin <pin name> is <delay value> ns
    1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
Shortest tpd from source pin <pin name> to destination pin <pin name> is <delay value> ns
    1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>

You can eliminate false source and destination paths from the timing analysis by turning on options when you specify project-wide timing requirements and/or by assigning the cut timing path assignment to an individual node by following the steps in making individual timing assignments.

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