See Also

Displays the frequency requirements and reports the worst-case speed performance (f_MAX) of the specified clock signal, as determined by the Timing Analyzer. The fmax section reports essentially the same data as the Register-to-Register Fmax section (Compilation Report), except the data is organized differently. The f_MAX timing information is displayed in a resizable, multicolumn table. You can click the + icon next to the clock name to expand the table and list, by default, the ten slowest destination registers associated with the clock, the ten slowest source registers associated with each destination register, the f_MAX requirements for the registers, and the minimum speed performance of the registers. The parenthetical note in the fmax section heading indicates whether the f_MAX calculations include delays to and from device pins, according to the options selected while specifying project-wide timing requirements. If you specify a default required f_MAX, and the timing requirement is not achieved, the timing information in those table rows appears in red.

If you specify any complex timing assignments, the Timing Analyzer reports the fMAX timing analysis results as slack in the Clock Requirement section (Compilation Report).

The following figure shows an excerpt of a sample fmax section:

You can select a clock or register name in the fmax section and choose List Paths (right button pop-up menu) to display the delay paths associated with the selected item. When you choose the List Paths command, the Messages window displays the time increments that comprise the delay path for the clock or register. You can locate to the source of a delay path in the Last Compilation floorplan by double-clicking the delay path message in the Messages window. The delay path information is displayed using the following syntax:

Internal fmax for clock <clock name> between register <source register name> and register  <destination register name> is <fmax value> MHz (Period:<clock period>ns)
    + Longest register to register delay is <delay value> ns
        1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    - Smallest Clock skew is <clock skew value> ns
        + Shortest Clock path from <clock name> to destination register is <delay value> ns
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
        - Longest Clock path from <clock name> to source register is <delay value> ns
            1:+ IC(<interconnect delay>) + CELL(<cell delay>) = <cumulative delay>;Loc. =  <location>; <node type> = <node name>
    + Micro clock to output delay of source register is <delay value> ns
    + Micro setup delay of destination register is <delay value> ns

The Timing Analyzer calculates the f_MAX using the following equations:

f_MAX = <register to register delay> - <clock skew delay> + <micro setup delay> + <micro clock to output delay>

The clock skew is calculated using the following equation:

<clock to destination register delay> - <clock to source register delay>

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