f_MAX

The maximum clock frequency that can be achieved without violating internal setup (t_SU) and hold (t_H) time requirements. The Quartus^® II software analyzes and reports "system" f_MAX and/or "internal" f_MAX. The calculation of system f_MAX includes any external delays to and from device pins; the calculation of internal f_MAX does not include any of these external delays.

You can specify the default required f_MAX for a design in the Clocks page of the Settings dialog box (Assignments menu). You can also specify the required f_MAX of individual clock signals in a design by creating clock settings and assigning them to signals in the design, as described in online Help in "Creating Clock Settings" and "Assigning Clock Settings to a Clock Signal," respectively.

The Timing Analyzer calculates the internal f_MAX using the following equations:

f_MAX = 1/(<register to register delay> - <clock skew delay> + <micro setup delay> + <micro clock to output delay>)

Where clock skew delay is calculated with the following equation:

<clock to destination register delay> - <clock to source register delay>

The Timing Analyzer calculates the system f_MAX, which includes external delays, using the following equation:

f_MAX = 1/(<register to register delay> - <clock skew delay> + <micro setup delay> + <micro clock to output delay> + <external input or output delay>)