The worst-case constraint (or requirement) that must be met to ensure that the correct data is available on a destination register in time for the register to latch the data.

In designs with multiple clocks, for every latch edge on the destination clock, the launching edge on the source register determines the delay requirement for the path. The following illustration shows a multiclock relationship in which RegA is feeding RegB. RegA is controlled by clk1 and RegB is controlled by clk2.

The following illustration shows the default setup relationship in a multiclock path from a clk1 register to a clk2 register.

You can override this default setup relationship in various ways by assigning any of the following timing assignments:

• Multicycle

• Source Multicycle

• Enable Multicycle

• Enable Source Multicycle

For example assigning a Multicycle assignment of 2 delays the latch edge by one clock period, as shown in the following illustration.

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