A multicycle path is one that requires more than one clock cycle to propagate.

In the Quartus^® II software, you can use the Assignment Organizer command (Assignments menu) to assign the Multicycle timing assignment, which allows you to change the setup relationship by specifying the number of clock cycles required before a register should latch a value. For example, assigning a Multicycle of 2 to a clocked register overrides the default setup relationship and delays the latch edge by one clock cycle. You can assign the Multicycle timing assignment to a destination register, or as a point-to-point assignment between two registers or clocks. Specifying a point-to-point Multicycle assignment may increase the time necessary for timing-driven compilation.