Specifies the maximum number of source clock cycles required before a register latches a value. When the source and destination clocks have different frequencies, this assignment allows you to increase the required setup relationship by adding source clock cycles. For example, assigning a Source Multicycle value of 2 to a clocked register overrides the default setup relationship and delays the latch edge by one clock cycle. The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on. Within a priority level, the most stringent requirement takes precedence. Specifying a point-to-point Source Multicycle assignment may increase the time necessary for timing-driven compilation.
| Priority Level | Assignment Type/Location | Affected Path(s) |
|---|---|---|
| 1 |
Point-to-point assignment from register to register. Point-to-point assignment from input or bidirectional pin to register. |
All data paths from the source to destination node. |
| 2 | Single-point assignment to any register. | All data paths terminating at the specified node. |
| 3 |
Point-to-point assignment from clock to clock. |
All paths with source clocked by |
| 4 | Single-point assignment to any clock. | All paths with destination clocked by clk1. |
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