Procedures

Commands

See Also

Timing requirements allow you to specify the desired speed performance for the entire project, for specific design entities, or for individual nodes and pins. If you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals when you use timing-driven compilation.

You can use the Timing wizard to easily specify all project-wide timing settings, including the minimum acceptable clock frequency (f_MAX), the maximum acceptable clock setup time (t_SU), hold time (t_H), clock-to-output delay (t_CO), and input-to-non-registered-output delay (t_PD). Alternatively, you can also use the Settings command (Assignments menu) to specify timing requirements and settings without using the wizard.

In addition, you can override the default timing requirements on specific portions of the design by creating clock settings and/or making individual timing assignments. You can also assign other individual timing assignments to cut timing paths, add external input or output delays, and invert clocks to further optimize your design. If you specify both individual and project-wide timing requirements, the Compiler uses the most stringent requirements.

After compilation, you can view the results of timing analysis to determine whether timing requirements were met, and then list and locate timing paths to debug delays in the critical path. You can also use the Timing Closure floorplan to view critical paths based on critical path settings you specify, and to view routing congestion based on routing congestion settings you specify.

	More information is available on Timing Analysis on the Altera® web site.

Back to Top