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During timing-driven compilation, the Fitter optimizes the placement of logic elements in a device to meet any specified timing requirements and timing assignments. The time spent in each iteration of timing analysis depends upon the type of timing assignments in the project. Certain types of timing assignments and assignment combinations may increase the time necessary to complete timing-driven compilation. To reduce the time required to complete timing-driven compilation, use the following guidelines when making timing assignments.

• The Timing Analyzer analyzes all timing assignments that have the same assignment name and value simultaneously. Therefore, when practical, it is best to reduce the number of timing assignments of the same type that have a different value. For example, the following Multicycle assignments are all analyzed simultaneously:

  reg -> reg2 : MULTICYCLE = 2
  reg3 -> reg4 : MULTICYCLE = 2
  reg5 -> reg6 : MULTICYCLE = 2
  

  Conversely, the following assignments each require a separate analysis, resulting in longer total compilation time:

  reg -> reg2 : MULTICYCLE = 2
  reg3 -> reg4 : MULTICYCLE = 3
  reg5 -> reg6 : MULTICYCLE = 4
  

• When the project contains multiple timing assignments with the same name and value, the Timing Analyzer analyzes assignments with the same source nodes simultaneously. Therefore, when practical, it is best to reduce the number of assignments of the same name and value that have different source nodes. For example, if a design has the following four paths, each sharing the COMB node, and has the following t_SU Requirement assignments,

  src1 -> dst1 : TSU =2ns
  src1 -> dst2 : TSU =2ns
  src2 -> dst1 : TSU =2ns
  src2 -> dst2 : TSU =2ns
  

  the Timing Analyzer reduces these assignments to the following subgroup, which it can analyze simultaneously:

  {{src1, src2} -> {dst1, dst2}}
  

  Conversely, if the same design has the following t_SU assignments,

  src2 -> dst1 : TSU = 2ns
  src1 -> dst2 : TSU = 2ns
  

  the Timing Analyzer creates the assignment subgroups {src1 -> dst2} and {src2 -> dst1}, which must be analyzed individually.

• Any point-to-point Cut Timing Path assignment slows down the Timing Analyzer during timing-driven compilation. Therefore, you can improve timing-driven compilation time by eliminating any unnecessary point-to-point Cut Timing Path assignments.

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