Procedures

Commands

See Also

You can also specify all timing settings outside the wizard by following the procedures described in Creating Clock Settings, Cutting Timing Paths, Specifying Default External Delays, and Specifying Project-Wide Timing Requirements.

The Timing Wizard (Assignments menu) helps you enter one or more of the following timing requirements and timing analysis settings:

• You can specify requirements for an overall circuit frequency (f_MAX), or specify requirements for one or more clock signals.

• You can enter project-wide system setup time (t_SU), hold time (t_H), clock-to-output time (t_CO), and pin-to-pin time (t_PD) requirements.

• You can specify default external delays to and from device pins.

• You can enter settings to control timing analysis and timing-driven compilation.  Guidelines

The timing requirements that you enter for pins and nodes are saved in the Entity Settings File (.esf) for the top-level entity in the current hierarchy.

You can change the timing settings by running the Timing wizard again, or change these and other timing settings with the Settings command (Assignments menu) and/or Assignment Organizer command (Assignments menu). For example, you can enter timing requirements for specific nodes and pins with the Assignment Organizer command (Assignments menu).

If you are creating a design that uses ClockLock® phase-locked loop (PLL) circuitry, you can use this wizard to enter the input frequency for the clock pin. To enter other information, such as the output frequencies of the ClockLock PLL, you must use the MegaWizard® Plug-In Manager (Tools menu) to create a custom megafunction variation of the altclklock megafunction with the appropriate settings.

	More information is available on Timing Analysis on the Altera® web site.

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