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Parameterized phase-locked loop (PLL) megafunction. The altclklock megafunction enables ClockLock® PLL circuitry. The phase-locked loop is used to synthesize a clock signal that is based on a reference clock. The altclklock megafunction can reduce clock delay and skew, and can be used to generate internal clocks that operate at frequencies that are multiples of the frequency of the system clock. The altclklock megafunction can also improve setup and hold times. The ACEX® 1K and FLEX 10KE PLL is capable of providing a x1 or x2 output clock that is synchronized to the reference input clock. The APEX™ 20K PLL is capable of providing a x1, x2, or x4 output clock that is synchronized to the reference input clock. The APEX 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, and Mercury™ PLL is more complex than the APEX 20K PLL, and has the ability to simultaneously multiply and divide the reference clock, provide an arbitrary phase shift, provide an external clock, and synchronize via an external feedback input. For Cyclone™, Stratix™, and Stratix™ GX designs, use the altpll megafunction to take advantage of the Cyclone and Stratix PLL features.
Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.
This topic contains the following information:
FUNCTION altclklock(inclock, inclocken, fbin)
WITH (INCLOCK_PERIOD, INCLOCK_SETTINGS,
VALID_LOCK_CYCLES, INVALID_LOCK_CYCLES,
VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER,
OPERATION_MODE,
CLOCK0_BOOST, CLOCK0_DIVIDE, CLOCK0_SETTINGS,
CLOCK1_BOOST, CLOCK1_DIVIDE, CLOCK1_SETTINGS,
OUTCLOCK_PHASE_SHIFT, CLOCK0_TIME_DELAY,
CLOCK1_TIME_DELAY, CLOCK2_BOOST, CLOCK2_DIVIDE,
CLOCK2_SETTINGS, CLOCK2_TIME_DELAY, CLOCK_EXT_BOOST,
CLOCK_EXT_DIVIDE, CLOCK_EXT_SETTINGS, CLOCK_EXT_TIME_DELAY,
INTENDED_DEVICE_FAMILY)
RETURNS (clock0, clock1, locked, clock2, clock_ext);
COMPONENT altclklock
GENERIC (INCLOCK_PERIOD: NATURAL := 10000;
INCLOCK_SETTINGS: STRING := "UNUSED";
VALID_LOCK_CYCLES: NATURAL := 5;
INVALID_LOCK_CYCLES: NATURAL := 5;
VALID_LOCK_MULTIPLIER: NATURAL := 1;
INVALID_LOCK_MULTIPLIER: NATURAL := 1;
OPERATION_MODE: STRING := "NORMAL";
CLOCK0_BOOST: NATURAL := 1;
CLOCK0_DIVIDE: NATURAL := 1;
CLOCK1_BOOST: NATURAL := 1;
CLOCK1_DIVIDE: NATURAL := 1;
CLOCK2_BOOST: NATURAL := 1;
CLOCK2_DIVIDE: NATURAL := 1;
CLOCK_EXT_BOOST: NATURAL := 1;
CLOCK_EXT_DIVIDE: NATURAL := 1;
CLOCK0_SETTINGS: STRING := "UNUSED";
CLOCK1_SETTINGS: STRING := "UNUSED";
CLOCK2_SETTINGS: STRING := "UNUSED";
CLOCK_EXT_SETTINGS: STRING := "UNUSED";
CLOCK0_TIME_DELAY: STRING := 0;
CLOCK1_TIME_DELAY: STRING := 0;
CLOCK2_TIME_DELAY: STRING := 0;
CLOCK_EXT_TIME_DELAY: STRING := 0;
OUTCLOCK_PHASE_SHIFT: NATURAL := 0);
PORT (inclock: IN STD_LOGIC;
inclocken, fbin : IN STD_LOGIC := '1';
clock0, clock1, clock2, clock_ext, locked : OUT STD_LOGIC);
END COMPONENT;
LIBRARY altera_mf USE altera_mf.altera_mf_components.all;
INPUT PORTS
| Port Name | Required | Description | Comments |
|---|---|---|---|
inclock |
Yes | The clock port that drives this ClockLock PLL. | |
inclocken |
No | The PLL enable signal. | When the inclocken port is high, the PLL drives the clock0 and clock1 ports. When the inclocken port is low, GND drives the clock0 and clock1 ports and the PLL goes out of lock. When the inclocken port goes high again, the PLL must relock. This port must be unconnected for ACEX 1K, APEX 20K, and FLEX 10KE devices. |
fbin |
No | The external feedback input for the PLL. | To complete the feedback loop, there must be a board-level connection between the fbin pin and the external clock output pin of the PLL. This port must be unconnected for ACEX 1K, APEX 20K, and FLEX 10KE devices. |
OUTPUT PORTS
| Port Name | Required | Description | Comments |
|---|---|---|---|
clock0 |
No | The first clock output of the PLL. | In ACEX 1K and FLEX 10KE devices, if the clock0 port is specified, the clock1 port must also be specified, and the value of the CLOCK1_BOOST parameter must be 2. In APEX 20K devices, if the pin driving
the inclock port of the PLL is used elsewhere in the design,
you can use only the clock0 output port of the PLL. No fit
is possible if you simultaneously use the clock0 port, clock1
port, and the pin driving the inclock port of the PLL. In APEX 20KC, APEX 20KE, APEX II, and ARM-based Excalibur
devices, you can use any two of the clock0 port, clock1 port,
and the pin driving the inclock port of the PLL. In Mercury
devices, you can use the clock1 port, clock2 port,
clock_ext port, and either the clock0 port or
the pin driving the inclock port of the PLL. If, however, you
are using the PLL to generate only one clock signal, when possible, you should
use the clock1 port to give the Compiler added flexibility
when fitting the PLL. |
clock1 |
No | The second clock output of the PLL. | In ACEX 1K and FLEX 10KE devices the CLOCK1_BOOST parameter must be set to 1 or 2, and the CLOCK1_DIVIDE parameter must be set to 1. In APEX 20K devices, if the pin driving
the inclock port of the PLL is used elsewhere in the design,
you can use only the clock0 output port of the PLL. No fit
is possible if you simultaneously use the clock0 port, clock1
port, and the pin driving the inclock port of the PLL. In APEX 20KE, APEX 20KC, APEX II, and ARM-based Excalibur,
devices, you can use any two of the clock0 port, clock1 port,
and the pin driving the inclock port of the PLL. In Mercury
devices, you can use the clock1 port, clock2 port,
clock_ext port, and either the clock0 port or
the pin driving the inclock port of the PLL. If, however, you
are using the PLL to generate only one clock signal, when possible, you should
use the clock1 port to give the Compiler added flexibility
when fitting the PLL. |
clock2 |
No | The third clock output of the PLL. | You can use the clock1 port, clock2 port,
clock_ext port, and either the clock0 port or
the pin driving the inclock port of the PLL. If, however, you
are using the PLL to generate only one clock signal, when possible, you should
use the clock1 port to give the Compiler added flexibility
when fitting the PLL. This port is available only for Mercury devices. |
clock_ext |
No | The clock output that drives out of the device. | The clock_ext port is the only output port that can drive a pin. This port must be connected to an output pin, and must be connected if the OPERATION_MODE parameter is set to ZERO_DELAY_BUFFER or EXTERNAL_FEEDBACK. This port is available only for Mercury devices. |
locked |
No | Gives the status of the PLL. | When the PLL is locked, this signal is VCC.
When the PLL is out of lock, this signal is GND. The locked
port may pulse high and low while the PLL is in the process of achieving
lock. |
| Parameter | Type | Required | Description |
|---|---|---|---|
INCLOCK_PERIOD |
Integer | No | Specifies the period of the inclock
port in ps. This parameter is
not required if a Clock Settings assignment is specified for the inclock
port. This port is required for simulation with other EDA simulators. |
INCLOCK_SETTINGS |
String | No | Specifies the Clock Settings assignment to be
used with the inclock port. If the INCLOCK_SETTINGS
parameter is specified, the INCLOCK_PERIOD parameter is not
required and is ignored. If omitted, the default is "UNUSED". |
VALID_LOCK_CYCLES |
Integer | No | Specifies the number of half-clock cycles for
which the clock output ports must be locked before the locked
pin goes high. This parameter is used only for third-party and functional
simulation. To compute the actual number of half-clock cycles for which
the clock output ports must be locked before the locked pin
goes high, the Compiler uses the value of the VALID_LOCK_MULTIPLIER
parameter. The computed value replaces any manually specified values for
the VALID_LOCK_CYCLES parameter. Altera recommends creating
the PLL with the MegaWizard Plug-In Manager (Tools menu) to obtain and select,
based on the design, a close approximation of the value of the VALID_LOCK_CYCLES
parameter. The MegaWizard Plug-In Manager automatically specifies
values for both the VALID_LOCK_CYCLES and VALID_LOCK_MULTIPLIER
parameters. If omitted, the default is 5. This parameter is
available only for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
INVALID_LOCK_CYCLES |
Integer | No | Specifies the number of half-clock cycles for
which the clock output ports must be out of lock before the locked
pin goes low. This parameter is used only for third party and functional
simulation. To compute the actual number of half-clock cycles for which
the clock output ports must be out of lock before the locked
pin goes low, the Compiler uses the value of the INVALID_LOCK_MULTIPLIER
parameter. The computed value replaces any manually specified values for
the INVALID_LOCK_CYCLES parameter. Altera recommends creating
the PLL with the MegaWizard Plug-In Manager to obtain and select,
based on the design, a close approximation of the value of the INVALID_LOCK_CYCLES
parameter. The MegaWizard Plug-In Manager automatically specifies
values for both the INVALID_LOCK_CYCLES and INVALID_LOCK_MULTIPLIER
parameters. If omitted, the default is 5. This parameter is
available only for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
VALID_LOCK_MULTIPLIER |
Integer | No | Specifies the scaling factor, in half-clock cycles,
for which the clock output ports must be locked before the locked
pin goes high. The Compiler uses the value of the VALID_LOCK_MULTIPLIER
parameter to compute the value of the VALID_LOCK_CYCLES parameter.
Altera recommends creating the PLL with the MegaWizard Plug-In Manager
to obtain and select, based on the design, a close approximation of the
scaling factor. The MegaWizard Plug-In Manager automatically specifies
values for both the VALID_LOCK_CYCLES and VALID_LOCK_MULTIPLIER
parameters. This parameter is required if the locked port is
connected. Values are 1 and 5. If omitted, the
default is 5. This parameter is available only for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
INVALID_LOCK_MULTIPLIER |
Integer | No | Specifies the scaling factor, in half-clock cycles,
for which the clock output ports must be out of lock before the locked
pin goes low. The Compiler uses the value of the INVALID_LOCK_MULTIPLIER
parameter to compute the value of the INVALID_LOCK_CYCLES parameter.
Altera recommends creating the PLL with the MegaWizard Plug-In Manager
to obtain and select, based on the design, a close approximation of the
scaling factor. The MegaWizard Plug-In Manager automatically specifies
values for both the INVALID_LOCK_CYCLES and INVALID_LOCK_MULTIPLIER
parameters. This parameter is required if the locked port is
connected. Values are 1 and 5. If omitted, the
default is 5. This parameter is available only for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
OPERATION_MODE |
String | No | In NORMAL mode, the phase shift
is measured between the internal clock network and the dedicated inclock
pin. If the PLL also feeds an external CLKLK_OUT pin, a phase
error results at the output of the external CLKLK_OUT pin due
to the time delay it introduces. In ZERO_DELAY_BUFFER mode,
the PLL behaves as a zero delay buffer of the input clock. The PLL must
be connected to an external CLKLK_OUT pin, and the output of
the external CLKLK_OUT pin is in phase with the dedicated inclock
pin. In APEX 20K, APEX II, and ARM-based Excalibur devices, if the clock0 port is used
to drive the external CLKLK_OUT pin, the CLOCK0_BOOST
parameter must be unused or set to 1; if the clock1
port is used to drive the external CLKLK_OUT pin, the CLOCK1_BOOST
parameter must be unused or set to 1. If the PLL is also used to drive the
internal clock network, a corresponding phase shift of that network results.
The programmable phase shift feature is not available in this mode, therefore
the OUTCLOCK_PHASE_SHIFT parameter must be unused or set to
0. In EXTERNAL_FEEDBACK mode, the fbin port must
be used, and a board-level connection between the external CLKLK_OUT
pin and the CLKLK_FB pin must exist. In addition, the PLL adjusts
its output to cause the signal observed at the CLKLK_FB pin
to be synchronized with the input clock. If the PLL is also used to drive
the internal clock network, a corresponding phase shift on that network
results. Values are "NORMAL", "ZERO_DELAY_BUFFER",
"EXTERNAL_FEEDBACK", and "LVDS". If omitted,
the default is "NORMAL". In Mercury devices, if the
OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK,
you cannot use any of the CLOCK<value>_TIME_DELAY
parameters on an external clock port; therefore, the CLOCK<value>_TIME_DELAY
parameter must be unused or set to 0. The LVDS setting is not available for Mercury devices. This parameter is available only for
APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
CLOCK0_BOOST |
Integer | No | Specifies the integer multiplication factor,
which must be greater than 0, for the clock0 port
with respect to the input clock frequency. This parameter can be specified
only if the clock0 port is used; however, it is not required
if a Clock Settings assignment is specified for the clock0 port. The value
for this parameter must be 1, 2, or 4
for APEX 20K devices. For ACEX 1K and FLEX 10KE devices, the value for this parameter must be 1. Create the PLL with the MegaWizard Plug-In
Manager to calculate the value for this parameter for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. If omitted, the default is 1. |
CLOCK0_DIVIDE |
Integer | No | Specifies the integer division factor, which
must be greater than 0, for the clock0 port with
respect to the input clock frequency. This parameter can be specified only
if the clock0 port is used; however, it is not required if
a Clock Settings assignment is specified for the clock0 port. The setting
for this parameter must be 1 for ACEX 1K, APEX 20K, and FLEX 10KE devices. Create
the PLL with the MegaWizard Plug-In Manager to calculate the value
for this parameter for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. If omitted, the
default is 1. |
CLOCK0_SETTINGS |
String | No | Specifies the Clock Settings assignment to be
used with the clock0 port. If this parameter is specified,
the CLOCK0_BOOST, CLOCK0_DIVIDE, and OUTCLOCK_PHASE_SHIFT
parameters are not required and are ignored. If more than one of the CLOCK<value>_SETTINGS
parameters are specified, they must have the same
phase shift. If omitted, the default is "UNUSED". |
CLOCK0_TIME_DELAY |
Integer | No | Specifies, in picoseconds (ps), a delay value to be applied to the clock0 port. The CLOCK0_TIME_DELAY parameter affects only the clock0 port and is independent of the OUTCLOCK_PHASE_SHIFT parameter; therefore, the two ports can be used simultaneously. Legal values range from -2000 ps through 2000 ps in increments of 250 ps. This parameter is available only for Mercury devices. |
CLOCK1_BOOST |
Integer | No | Specifies the integer multiplication factor,
which must be greater than 0, for the clock1 port
with respect to the input clock frequency. This parameter can be specified only
if the clock1 port is used; however, it is not required if
a Clock Settings assignment is specified for the clock1 port. The setting
for this parameter must be 1 or 2 for ACEX 1K and FLEX 10KE devices. The setting
for this parameter must be 1, 2, or 4
for APEX 20K devices. Create the PLL with the MegaWizard Plug-In
Manager to calculate the value for this parameter for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. If omitted, the default is 1. |
CLOCK1_DIVIDE |
Integer | No | Specifies the integer division factor, which
must be greater than 0, for the clock1 port with
respect to the input clock frequency. The parameter can be specified only
if the clock1 port is used; however, it is not required if
a Clock Settings assignment is specified for the clock1 port. Create
the PLL with the MegaWizard Plug-In Manager to calculate the value
for this parameter for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. If omitted,
the default is 1. |
CLOCK1_SETTINGS |
String | No | Specifies the Clock Settings assignment to be
used with the clock1 port. If this parameter is specified,
the CLOCK1_BOOST, CLOCK1_DIVIDE, and OUTCLOCK_PHASE_SHIFT
parameters are not required and are ignored. If more than one of the CLOCK<value>_SETTINGS
parameters are specified, they both must have the
same phase shift. If omitted, the default is "UNUSED". |
CLOCK1_TIME_DELAY |
String | No | Specifies, in picoseconds (ps), a delay value to be applied to the clock1 port. The CLOCK1_TIME_DELAY parameter affects only the clock1 port and is independent of the OUTCLOCK_PHASE_SHIFT parameter, therefore, the two ports can be used simultaneously. Legal values range from -2000 ps through 2000 ps in increments of 250 ps. This parameter is available only for Mercury devices. |
CLOCK2_BOOST |
Integer | No | Specifies the integer multiplication factor,
which must be greater than 0, for the clock2 port
with respect to the input clock frequency. This parameter can be specified
only if the clock2 port is used; however, it is not required
if a Clock Settings assignment is specified for the clock2 port. Create the PLL with the MegaWizard Plug-In
Manager to calculate the value for this parameter. If omitted, the default is 1. This parameter is available only for Mercury devices. |
CLOCK2_DIVIDE |
Integer | No | Specifies the integer division factor, which
must be greater than 0, for the clock2 port with
respect to the input clock frequency. This parameter can be specified only
if the clock2 port is used; however, it is not required if
a Clock Settings assignment is specified for the clock2 port. Create
the PLL with the MegaWizard Plug-In Manager to calculate the value
for this parameter. If omitted, the
default is 1. This parameter is available only for Mercury devices. |
CLOCK2_SETTINGS |
Integer | No | Specifies the Clock Settings assignment to be
used with the clock2 port. If this parameter is specified,
the CLOCK2_BOOST, CLOCK2_DIVIDE, and OUTCLOCK_PHASE_SHIFT
parameters are not required and are ignored. If more than one of the CLOCK<value>_SETTINGS
parameters are specified, they both must have the same
phase shift. If omitted, the default is "UNUSED". This parameter is available only for Mercury devices. |
CLOCK2_TIME_DELAY |
String | No | Specifies, in picoseconds (ps), a delay value to be applied to the clock2 port. The CLOCK2_TIME_DELAY parameter affects only the clock2 port and is independent of the OUTCLOCK_PHASE_SHIFT parameter; therefore, the two ports can be used simultaneously. Legal values range from -2000 ps through 2000 ps in increments of 250 ps. This parameter is available only for Mercury devices. |
CLOCK_EXT_BOOST |
Integer | No | Specifies the integer multiplication factor,
which must be greater than 0, for the clock_ext port
with respect to the input clock frequency. This parameter can be specified
only if the clock_ext port is used; however, it is not required
if a Clock Settings assignment is specified for the clock_ext port. Create the PLL with the MegaWizard Plug-In
Manager to calculate the value for this parameter. If omitted, the default is 1. This parameter is available only for Mercury devices. |
CLOCK_EXT_DIVIDE |
Integer | No | Specifies the integer division factor, which
must be greater than 0, for the clock_ext port with
respect to the input clock frequency. This parameter can be specified only
if the clock_ext port is used; however, it is not required if
a Clock Settings assignment is specified for the clock_ext port. Create
the PLL with the MegaWizard Plug-In Manager to calculate the value
for this parameter. If omitted, the
default is 1. This parameter is available only for Mercury devices. |
CLOCK_EXT_SETTINGS |
String | No | Specifies the Clock Settings assignment to be
used with the clock_ext port. If this parameter is specified,
the CLOCK_EXT_BOOST, CLOCK_EXT_DIVIDE, and OUTCLOCK_PHASE_SHIFT
parameters are not required and are ignored. If more than one of the CLOCK<value>_SETTINGS
parameters are specified, they must have the same
phase shift. If omitted, the default is "UNUSED". This parameter is available only for Mercury devices. |
CLOCK_EXT_TIME_DELAY |
String | No | Specifies, in picoseconds (ps), a delay value to be applied to the clock_ext port. The CLOCK_EXT_TIME_DELAY parameter affects only the clock_ext port and is independent of the OUTCLOCK_PHASE_SHIFT parameter; therefore, the two ports can be used simultaneously. Legal values range from -2000 ps through 2000 ps in increments of 250 ps. This parameter is available only for Mercury devices. |
OUTCLOCK_PHASE_SHIFT |
Integer | No | Specifies, in picoseconds (ps), the phase shift of
the output clocks relative to the input clock. Phase shifts of 0.0, 0.25,
0.5, or 0.75 times the input period (0, 90, or 270 degrees) are implemented
precisely. The allowable range for the phase shift is between 0 ps and one
input clock period. If the phase shift is outside this range, the Compiler
adjusts it to fall within this range. For other phase shifts, the Compiler
chooses the closest allowed value. This parameter is not required, and is ignored, if any
of the CLOCK<value>_SETTINGS parameters
are used. If omitted, the default is 0. ClockShift™ circuitry
allows you to adjust clock delay or phase for precise timing. This parameter
is available only if the OPERATION_MODE parameter is set to
NORMAL, and only for APEX 20KC, APEX 20KE, APEX II, ARM-based Excalibur, and Mercury devices. |
INTENDED_DEVICE_FAMILY |
String | No | This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard Plug-in Manager to calculate the value for this parameter. |
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