A feature available in selected ACEX^® 1K, APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, FLEX 10KE, and Mercury^™ devices that employs a phase-locked loop (PLL). The ClockLock^® circuitry can be used to reduce clock delay and skew and can also generate internal clocks that operate at frequencies that are multiples of the frequency of the system clock. This reduction minimizes clock-to-output and setup times while maintaining zero hold times.

You can take advantage of the ClockLock feature by using the altclklock megafunction.

Also referred to as General-Purpose PLL (GPLL).