Overviews

Commands

See Also

To specify whether the Compiler or Simulator should process the Verilog Design File(s) (.v) using Verilog HDL version 1995 or Verilog HDL version 2001:

1. If you have not already done so, create a new project or open an existing project.

2. Choose Settings (Assignments menu).

3. In the Category list, select Verilog HDL Input under HDL Input Settings.

4. Under Verilog version, select which version of Verilog HDL you want the Compiler or Simulator to use when processing Verilog HDL Design Files.

5. Click OK.

Back to Top