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To specify the Library Mapping File (.lmf) for the Compiler or Simulator to use when compiling or simulating Verilog Design Files (.v):

1. If you have not already done so, create a new project or open an existing project.

2. Choose Settings (Assignments menu).

3. In the Category list, select Verilog HDL Input under HDL Input Settings.

4. Under Library Mapping File, in the File name list, type the file directory and name of the LMF you want the Compiler or Simulator to use, or select the file and directory name with Browse (...).

5. If you want, under Library Mapping File, turn on Show information messages describing LMF mapping during compilation.

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