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Directs the Compiler or Simulator to process Verilog HDL Design Files (.v) using the specified standard. You can select one of the following options:
| Verilog-1995 | Directs the Compiler or Simulator to process Verilog HDL Design Files using the IEEE Std 1364-1995 Verilog HDL standard. |
| Verilog-2001 | Directs the Compiler or Simulator to process Verilog HDL Design Files using the IEEE Std 1364-2001 Verilog HDL standard. By default, this option is selected. |
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- PLDWorld - |
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