See Also

Directs the Compiler to output the Excalibur^™ embedded processor stripe as a single entity in a VHDL Output File (.vho) or as a single module in a Verilog Output File (.vo) for an ARM^®-based Excalibur design.

You should turn this option on if you want to perform a full stripe model simulation, simulating the embedded processor core and dual-port SRAM or single-port SRAM as a single entity or module. Turn this option off if you want to perform a bus functional model simulation, simulating the embedded processor core and dual-port SRAM or single-port SRAM as separate entities or modules.

This option should be turned off if you want to simulation of the design, but should be turned on for a of the design.

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