The bus functional model emulates the behavior of the AMBA^™ high-performance bus (AHB) in the Excalibur^™ embedded processor stripe of an ARM^®-based Excalibur device. It simulates the interactions between the Excalibur embedded processor stripe and the PLD over the Stripe-to-PLD Bridge via the Stripe Master-Port and over the PLD-to-Stripe Bridge via the Stripe Slave-Port.

To use the bus functional model for a functional or timing simulation using other EDA tools, you must create the bus functional model simulation files and place them in the simulation directory. For stripe to PLD bus transactions, you must generate a mastercommands.dat file, which describes the read, write, wrapping, and incremental burst options, as well as busy and idle transactions and periods of idleness that are initiated by the embedded processor core and directed to the PLD. For PLD to stripe bus transactions, you must create a slavememory.cfg.dat file, which specifies up to six memory banks in the stripe, and the corresponding slavememory.<bank number>.dat files, which specify the initial contents of the memory spaces (SDRAM Interface, Expansion Bus Interface, UART Interface, and so on) in the stripe.

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