An ASCII file (with the extension .pwf) that is generated by the ModelTech ModelSim^® software for performing power estimation with the Quartus^® II software. The Power Input File contains the input signals and logic levels of the design.

To specify that the ModelSim software should generate the Power Input File during simulation, turn on Generate Power Input File in the Verilog HDL/VHDL Output Settings dialog box, which is available from the EDA Tool Settings page of the Settings dialog box. The Quartus II software adds the necessary information to create the Power Input File into the Verilog Output File or VHDL Output File for the design. After the design is simulated with the ModelSim software, the Power Input File is generated and placed in the \<project directory>\simulation\modelsim directory.

Once the Power Input File is generated, you can specify that the Quartus II software should use the Power Input File as a vector source file during simulation in the Time/Vectors page of the Settings dialog box (Assignments menu).

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