An ASCII text file (with the extension .vt) that is generated by the Quartus^® II software or with the Quartus II Text Editor or any other standard text editor. A Verilog Test Bench File contains an instantiation of the top-level design entity for a design and simulation input vectors and simulation output vectors. You can use a Verilog Test Bench File for simulation of a design with other EDA tools.

You can create a Verilog Test Bench File from a vector source file in the Quartus II software by choosing the Export command (File menu) and exporting the file as a Verilog Test Bench File. You can also generate a template for a Verilog Test Bench File by compiling a design and choosing the EDA Tools Post Compilation Commands > Generate Test Bench Template command (Processing menu), which places the template in the /<project directory>/simulation/<EDA simulation tool> directory.

A Verilog Test Bench File is the same as a standard Verilog HDL test bench file, saved with a .vt extension.

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